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19-4614; Rev 0; 4/09
Z86L88
Low-Voltage IR Microcontroller
Product Specification
Maxim Integrated Products Inc. 120 San Gabriel Drive, Sunnyvale CA 94086
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States 408-737-7600 www.maxim-ic.com
Copyright (c) 2009 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Maxim is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc.
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Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 (P07-P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 (P27-P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 (P37-P31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Register (SMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Register 2 (SMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Mode Register (WDTMR) . . . . . . . . . . . . . . . . . . . . . . . . Mask Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 13 15 16 17 17 19 19 19 19 32 33 34 43 54 56 57 58 58 59 59 64 65 68
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Z86L88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Customer Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 28-Pin DIP/SOIC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Memory Map (16K ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TC8 Control Register--(0D) OH: Read/Write Except Where Noted . . . . . . . . . . . . 22 T8 and T16 Common Control Functions--(0D) 1H: Read/Write . . . . . . . . . . . . . . . 23 T16 Control Register--(0D) 2H: Read/Write Except Where Noted . . . . . . . . . . . . 24 Stop-Mode Recovery Register--(0F) 0BH: D6-D0 = Write Only, D7 = Read Only 25 Stop-Mode Recovery Register 2--(0F) 0DH: D2-D4, D6 Write Only . . . . . . . . . . . 26 Watch-Dog Timer Register--(0F) 0FH: Write Only . . . . . . . . . . . . . . . . . . . . . . . . . 27 Port Configuration Register (PCON)--(0F) 0H: Write Only . . . . . . . . . . . . . . . . . . 27 Port 2 Mode Register--F6H: Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port 3 Mode Register--F7H: Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Port 0 and 1 Mode Register (F8h: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt Priority Register--F9H: Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt Request Register--FAH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt Mask Register--FBH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flag Register--FCH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register Pointer--FDH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Stack Pointer High--FEH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Stack Pointer Low--FFH: Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55.
T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration Register (PCON)--Write Only . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery Register 2--(0F) DH:D2-D4, D6 Write Only . . . . . . . . . . . . Watch-Dog Timer Mode Register--Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Codes Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47 48 49 50 51 51 53 54 55 57 59 60 60 62 64 66 67 69 70 71 72
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Z86L88 Features 1 Power Conventions 3 28-Pin DIP and SOIC Pin Identification 5 Absolute Maximum Ratings 6 Capacitance 7 DC Characteristics 8 AC Characteristics 11 Pin Assignments 17 Expanded Register Group D 34 HI8(D)0Bh 34 L08(D)0Ah 35 HI16(D)09h 35 L016(D)08h 35 TC16H(D)07h 35 TC16L(D)06h 36 TC8H(D)05h 36 TC8L(D)04h 36 CTR0 (D)00 Counter/Timer8 Control Register 37 CTR1(D)01h Register 39 CTR2 (D)02h: Counter/Timer16 Control Register 42 Interrupt Types, Sources, and Vectors 55 IRQ Register * 56 Stop-Mode Recovery Source 63 SMR2(F)0Dh: Stop-Mode Recovery Register 2 65 WDT Time Select* 66 Mask Selectable Options 68
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Z86L88 Low-Voltage IR Microcontroller
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Features
Table 1 lists some of the features of the Z86L88 microcontroller.
Table 1. Z86L88 Features Device Z86L88 ROM (KB) 16 RAM* (Bytes) 237 I/O Lines 23 Voltage Range 2.0 V to 3.6 V
Note: *General purpose
* *
Low power consumption--40 mW (typical) Three standby modes - STOP--2 A (typical) - HALT--0.8 mA (typical) - Low voltage Special architecture to automate both generation and reception of complex pulses or signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception Five priority interrupts - Three external - Two assigned to counter/timers Low voltage protection Programmable watch-dog/power-on reset circuits Two independent comparators with programmable interrupt polarity Mask-selectable pull-up transistor on Ports 0, 2, and 3 Programmable mask options: - Oscillator selection: RC oscillator versus crystal or other clock source
*
* * * * * *
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- - - - - -
Oscillator operational mode: normal high-frequency operation enabled versus 32-KHz operation enabled Port 0: 0-3 pull-ups Port 0: 4-7 pull-ups Port 2: 0-7 pull-ups Port 3: pull-ups Port 0: 0-3 Mouse Mode: Normal Mode (.5VDD input threshold) versus Mouse Mode (.4VDD input threshold)
Note: The mask option pull-up transistor has a typical equivalent resistance of 200 K50% at VCC=3 V and 450 K50% at VCC=2 V.
General Description
The Z86L88 is a ROM-based member of the Z8 MCU single-chip family of infrared (IR) controllers, featuring 237 bytes of general-purpose RAM and 16 KB of ROM, respectively. Maxim's CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The Z86L88 architecture is based on Maxim's 8-bit microcontroller core featuring an Expanded Register File to allow access to register-mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z8 offers a flexible I/O scheme, an efficient register and address-space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and batteryoperated hand-held applications. Three basic address spaces are available to support a wide range of configurations: program memory, register file, and Expanded Register File. The register file consists of 256 bytes of RAM. It includes 4 I/O port registers, 16 control and status registers, and 236 general-purpose registers. [Register FEh (SPH) can be used as a general-purpose register.] The Expanded Register File consists of two additional register groups (F and D). The Z86L88 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages (see Figure 9 on page 18).
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HI 16 8
Lo 16 8
16-Bit T 16 1248 8 SCLK Clock Divider TC16H 16 8 TC16L And/Or Logic HI8 8 Input Glitch Filter Edge Detect Circuit LO8 8 8-Bit T8 8 TC8H 8 TC8L
Timer 16
Timer 8/16
Timer 8
Figure 1. Counter/Timers Diagram
Note: All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections follow the conventions listed in Table 2.
Table 2. Power Conventions Connection Power Ground Circuit VCC GND Device VDD VSS
Figure 2 shows the functional block diagram.
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P00 P01 P02 P03 P04 P05 P06 P07
4 Port 0 4 Register Bus ROM 16K x 8
Register File 256 x 8-Bit Port 3 Internal Address Bus Z8 Core Internal Data Bus Expanded Register Bus Machine Timing and Instruction Control
Pref1 P31 P32 P33 P34 P35 P36 P37
XTAL
I/O Bit Programmable P20 P21 P22 P23 P24 P25 P26 P27
Expanded Register File
Port 2 Counter/Timer 16 16-Bit
Power
VDD VSS
Counter/Timer 8 8-Bit
Figure 2. Functional Block Diagram
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Pin Description
The pin assignment for the 28-pin dual in-line package (DIP)/small outline integrated circuit (SOIC) is shown in Figure 3. The pins are identified in Table 3.
P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1
28
Z86L88 DIP/SOIC
14
15
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 Pref1 P36 P37 P35
Figure 3. 28-Pin DIP/SOIC Pin Assignment
Table 3. 28-Pin DIP and SOIC Pin Identification 28-Pin DIP and SOIC 19 20 21 23 4 5 6 7 24 25 26 27 28 1 2 3 18 Standard Mode P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 Pref1 Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Description Port 0 is nibble programmable. Port 0-3 can be configured as a mouse/trackball input.
Port 2 pins are individually configurable as input or output.
Analog ref input; connect to VCC if not used
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Table 3. 28-Pin DIP and SOIC Pin Identification (Continued) 28-Pin DIP and SOIC 11 12 13 14 15 17 16 10 9 8 22 Standard Mode P31 P32 P33 P34 P35 P36 P37 XTAL1 XTAL2 VDD VSS Direction Input Input Input Output Output Output Output Input Output Description IRQ2/modulator input IRQ0 IRQ1 T8 output T16 output T8/T16 output Crystal, oscillator clock Crystal, oscillator clock Power supply Ground
Absolute Maximum Ratings
Table 4 lists the absolute maximum ratings for the Z86L88 microcontroller.
Table 4. Absolute Maximum Ratings Symbol Vmax TSTG TA
Notes:
Description Supply Voltage (*) Storage Temperature Oper. Ambient Temperature
Min -0.3 -65
Max +7.0 +150
Units V C C
* Voltage on all pins with respect to GND See "Ordering Information" on page 69.
Stresses greater than those listed under Absolute Maximum Ratings might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability.
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Standard Test Conditions
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 4).
From Output Under Test
I
Figure 4. Test Load Diagram
Capacitance
Table 5 lists the capacitance for the Z86L88 microcontrollers.
.
Table 5. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
Note: TA = 25C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND.
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DC Characteristics
Table 6 lists the direct current (DC) characteristics.
Table 6. DC Characteristics TA = 0 C to +70 C VCC Min Max 2.0 V 7 3.6 V 7 2.0 V 0.8 VCC VCC + 0.3 3.6 V 0.8 VCC VCL Clock Input Low Voltage
Symbol Parameter Max Input Voltage VCH Clock Input High Voltage
Units V V V
VCC + 0.3 V V V V V V V V V V V V V V V V V mV mV
2.0 V VSS-0.3 0.2 VCC 3.6 V VSS-0.3 0.2 VCC
Conditions Notes IIN <250 A IIN <250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
VIH
2.0 V 3.6 V VIL Input Low Voltage 2.0 V 3.6 V VOH1 Output High Voltage 2.0 V 3.6 V VOH2 Output High Voltage 2.0 V (P00, P01, P36, and P37) 3.6 V VOL1 Output Low Voltage 2.0 V 3.6 V VOL2 Output Low Voltage 2.0 V 3.6 V VOL2 Output Low Voltage 2.0 V (P00, P01, P36, and P37) 3.6 V VOFFSET Comparator Input Offset Voltage 2.0 V 3.6 V IIL Input Leakage 2.0 V 3.6 V IOL Output Leakage 2.0 V 3.6 V
Input High Voltage
0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.8 VCC-0.8
VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC
-1 -1 -1 -1
0.4 0.4 0.8 0.8 0.8 0.8 25 25 1 1 1 1
IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH = -7 mA IOL = 1.0 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 7.0 mA IOL = 10 mA IOL = 10 mA
1
1 1
A A A A
VIN = 0 V, VCC VIN = 0 V, VCC VIN = 0 V, VCC VIN = 0 V, VCC
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Table 6. DC Characteristics (Continued) TA = 0 C to +70 C VCC Min Max 2.0 V 10 3.6 V 15 2.0 V 250 3.6 V 850 2.0 V 3 3.6 V 2.0 V 3.6 V 2.0 V 5 2 4 8
Symbol Parameter ICC Supply Current
ICC1
Standby Current (HALT Mode)
ICC2
Standby Current (STOP Mode)
3.6 V 2.0 V 3.6 V 2.0 V 12 3.6 V 5
10 500 800 75 20 2.0
TPOR VBO
Power-On Reset VCC Low Voltage Protection
Units Conditions mA at 8.0 MHz mA at 8.0 MHz A at 32 kHz A at 32 kHz mA VIN = 0 V, VCC at 8.0 MHz mA Same as above mA Clock Divide-by-16 at 8.0 MHz mA Same as above A VIN = 0 V, VCC WDT is not Running A Same as above A VIN = 0 V, VCC WDT is Running A Same as above ms ms V 8 MHz max Ext. CLK Freq.
Notes 2, 3 2, 3 2, 3, 8 2, 3, 8 2, 3 2, 3 2, 3 2, 3 4, 6, 9
4, 6, 9 4, 6, 9 4, 6, 9
5
Notes: 1. All outputs excluding P00, P01, P36, and P37 2. All outputs unloaded, inputs at rail 3. CL1 = CL2 = 100 pF 4. Same as note 2 except inputs at VCC 5. The VBO is measured at room temperature and typically is 1.6 V. VBO increases as the temperature decreases. 6. Oscillator stopped 7. Not applicable 8. 32-kHz clock driver input 9. WDT, Comparators, Low Voltage Detection, and ADC (if applicable) are disabled. The IC might draw more current if any of the above peripherals is enabled.
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AC Characteristics
This section discusses the alternating current (AC) characteristics. The timing diagram is shown in Figure 5 and described in Table 7.
1 3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Figure 5. Timing Diagram
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Table 7. AC Characteristics TA = 0C to +70C 8.0 MHz Number Symbol 1 TpC 2 3 4 5 6 7 8A 8B 9 10 11 TrC,TfC TwC TwTinL TwTinH TpTin Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 5.5 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V Min 121 121 Max DC DC 25 25 Stop-Mode Recovery (D1, D0) Units Notes ns 1 ns 1 ns 1 ns 1 ns 1 ns 1 ns 1 ns 1 1 1 1 1 ns 1 ns 1 ns 1, 2 ns 1, 2 1, 3 1, 3 1, 2 1, 2 ns ns 4 4
37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
TrTin,TfTin Timer Input Rise and Fall Times TwIL TwIL TwIH Twsm Tost Interrupt Request Low Time Interrupt Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec Oscillator Start-Up Time
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Table 7. AC Characteristics (Continued) TA = 0C to +70C 8.0 MHz Number Symbol 12 Twdt Parameter Watch-Dog Timer Delay Time VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V Min 20 7.5 20 7.5 40 15 160 60 Max Stop-Mode Recovery (D1, D0) Units Notes ms 5 0, 0 ms 5 ms 5 0, 1 ms 5 ms 5 1, 0 ms 5 ms 5 1, 1 ms 5
(60 ms)
Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31) 3. Interrupt request through Port 3 (P30) 4. SMR - D5 = 0. 5. For internal RC oscillator
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Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator input. An external single-phase clock to the on-chip oscillator input is also an option.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output.
Port 0 (P07-P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open drain controlled by bit D2 in the PCON register. If one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. A mask option is available to program 0.4 VDD CMOS trip inputs on P00-P03. This option allows direct interface to mouse/trackball IR sensors. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. See Figure 6. Note: Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode.
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4 Port 0 (I/O) Z86L88 MCU 4
Open-Drain I/O
Mask Option
VCC Resistive transistor pull-up
Pad
Out
In
In *Mask Selectable 0.4 VCC Trip Point Buffer
Figure 6. Port 0 Configuration
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Port 2 (P27-P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the 8 bits of Port 2 configured as inputs. Port 2 also has an 8-bit input OR and AND gate that can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in demodulation mode. See Figure 7.
Z86L88 MCU
Port 2 I/O
Open-Drain I/O
Mask Option
VCC Resistive transistor pull-up
Pad
Out
In
Figure 7. Port 2 Configuration
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Port 3 (P37-P31)
Port 3 (see Figure 8) is a 7-bit, CMOS-compatible, fixed I/O port. Port 3 consists of three fixed input (P33-P31) and four fixed output (P37-P34) ports, and each can be configured under software control for interrupt and output from the counter/timers. P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.
P31 Z86L88 MCU P32 P33 Port 3 (I/O) P34 P35 P36 P37
R247 = P3M D1 1 = Analog 0 = Digital
DIG. P31 (AN1) + Pref AN. - Comp1 IRQ2, P31 Data Latch
P32 (AN2) + P33 (Ref2) -
Comp1
IRQ0, P32 Data Latch
From Stop Mode Recovery Source of SMR
IRQ1, P33 Data Latch
Figure 8. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32 with reference to the voltage on Pref1 and P33. The analog function is enabled by
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programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge-triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the counter/timer edge-detection circuit is through P31 or P20 (see "Common Control Register to Counter/Timer T8 and T16" on page 39). Other edge-detect and IRQ modes are described in Table 8.
Table 8. Pin Assignments Pin Pref1 P31 P32 P33 P34 P35 P36 P37 P20 IN IN IN OUT OUT OUT OUT I/O IN T8 T16 T8/16 AO2 IN I/O C/T Comp. RF1 AN1 AN2 RF2 AO1 IRQ2 IRQ0 IRQ1 Int.
Port 3 also provides output for the counter/timers and the AND/OR logic. Control is performed by programming bits D5-D4 of CTR1, bit 0 of CTR0, and bit 0 of CTR2.
Comparator Inputs
In analog mode, P31 and P32 have a comparator front end. The comparator reference is supplied to Pref1 and P33. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 8 on page 16. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP Mode. For P31-P33 to be used in a Stop-Mode Recovery source, these inputs must be placed into digital mode.
Comparator Outputs
These outputs can be programmed to be output on P34 and P37 through the PCON register. See Figure 9.
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CTR0, D0
P34 data T8_Out MUX
PCON, D0 VDD
MUX P31 Pref1 + - Comp1 CTR2, D0 VDD Out 35 T16_Out MUX
Pad P34
Pad P35
CTR1, D6 VDD Out 36 MUX T8/16_Out Pad P36
PCON, D0 VDD P37 data MUX P32 Pref2 Pad
P37
+ - Comp2
Figure 9. Port 3 Counter/Timer Output Configuration
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Functional Description
The Z86L88 incorporates special functions to enhance the Z8's functionality in consumer and battery-operated applications.
Program Memory
The Z86L88 device addresses 16 KB of internal program memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the five 16-bit vectors that correspond to the five available interrupts.
RAM
The Z86L88 device has 237 bytes of RAM that make up the register file.
Not Accessible On-Chip ROM
12 11 10 9 8 7
16383
Location of First byte of Instruction Executed After RESET
Reset Start Address IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte)
6 5 4 3 2 1 0
Figure 10. Program Memory Map (16K ROM)
Expanded Register File
The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 through R15 has been implemented as
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16 banks with 16 registers per bank. These register groups are known as the Expanded Register File (ERF). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred to as an expanded register group (see Figure 11). The upper nibble of the register pointer (Figure 12 on page 22) selects which working register group is accessed of 16 bytes in the register file, out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Z86L88 device, banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed, but any other value from 1h to Fh exchanges the lower 16 registers to an expanded register bank. For example, for the Z86L88 (see Figure 11):
R253 RP R0 R1 R2 R3 = = = = = 00h Port Port Port Port 0 1 2 3
But if:
R253 RP R0 R1 R2 R3 = = = = = 0Dh CTRL0 CTRL1 CTRL2 Reserved
The counter/timers are mapped into ERF group D. Access is easily performed using the following:
LD LD LD LD LD LD RP, #0Dh R0,#xx 1, #xx R1, 2 RP, #0Dh RP, #7Dh ; ; ; ; ; ; ; ; ; ; ; ; Select ERF D for access to bank D (working register group 0) load CTRL0 load CTRL1 CTRL2CTRL1 Select ERF D for access to bank D (working register group 0) Select expanded register bank D working register group 7 of bank 0 for access. CTRL2register 71h CTRL2register 71h
LD LD
71h, 2 R1, 2
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Z8 Standard Control Registers REGISTER** REGISTER POINTER 7 6 5 4 3 2 1 0 FF FE FD Working Register Group Pointer Expanded Register Bank Group Pointer FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved 7
RESET CONDITION 6 5 4 3 2 1 0
UUUUUUUU UUUUUUUU 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 UUUUUUUU
UUUUUUUU
* *
Z8 Register File (Bank 0)** FF F0
UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU 0 0 0 0 0 0 0 0 0 0 0 0 0 UU0
EXPANDED REG. BANK (F) REGISTER**
RESET CONDITION UUU0 U0U0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
*
7F Reserved
(F) 0F (F) 0E (F) 0D (F) 0C
WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON
(F) 0B (F) 0A (F) 09 (F) 08
0F 00
Reserved
(F) 07 (F) 06 (F) 05 (F) 04 (F) 03 (F) 02 (F) 01 (F) 00
*
EXPANDED REG. GROUP (0) REGISTER**
UUUUUUUU RESET CONDITION
EXPANDED REG. BANK (D) REGISTER** RESET CONDITION 0U0UUUU
(D) 0C (D) 0B (D) 0A (D) 09 (D) 08 (D) 07 (D) 06 (D) 05 (D) 04 (D) 03
Reserved HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU 0 0 0 UUU UUU0 0 UU UUUU 0 UU UUU0
* *
(0) 03 (0) 02 (0) 00
P3 P2 P0
0
UUUUUUUU UUUUUUUU
U = Unknown * Not reset with a Stop-Mode Recovery ** All addresses are in hexadecimal Not reset with a Stop-Mode Recovery, except Bit 0.
(D) 02 (D) 01 (D) 00
Figure 11.
Expanded Register File Architecture
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R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register File Pointer Working Register Pointer
Default setting after reset = 0000 0000
Figure 12. Register Pointer Register
Expanded Register File Control Registers (0D) Figure 13, Figure 14, and Figure 15 show the expanded register file control registers (0D).
CTR1 (0D) 0H D7 D6 D5 D4 D3 D2 D1 D0 0 = P34 as Port Output * 1 = Timer8 Output 0 = Disable T8 Time-out Interrupt 1 = Enable T8 Time-out Interrupt 0 = Disable T8 Data Capture Interrupt 1 = Enable T8 Data Capture Interrupt 00 = SCLK on T8 01 = SCLK/2 on T8 10 = SCLK/4 on T8 11 = SCLK/8 on T8 R = 0 T8 No T8 Counter Time-out R = 1 T8 Counter Time-out Occurred W = 0 No Effect W = 1 Reset Flag to 0 0 = Modulo-N 1 = Single Pass R = 0 T8 Disabled * R = 1 T8 Enabled W = 0 Stop T8 W = 1 Enable T8
* Default setting after reset
Figure 13. TC8 Control Register--(0D) OH: Read/Write Except Where Noted
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CTR1 (0D) 1H D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode R/W 0 T16_OUT is 0 Initially 1 T16_OUT is 1 Initially Demodulation Mode R 0 = No Falling Edge Detection R 1 = Falling Edge Detection W 0 = No Effect W 1 = Reset Flag to 0 Transmit Mode R/W 0 = T8_OUT is 0 initially R/W 1 = T8_OUT is 1 initially Demodulation Mode R 0 = No Rising Edge Detection R 1 = Rising Edge Detection W 0 = No Effect W 1 = Reset flag to 0 Transmit Mode 0 0 = Normal Operation 0 1 = Ping-Pong Mode 1 0 = T16_OUT = 0 1 1 = T16_OUT = 1 Demodulation Mode 0 0 = No Filter 0 1 = 4 SCLK Cycle Filter 1 0 = 8 SCLK Cycle Filter 1 1 = Reserved Transmit Mode/T8/T16 Logic 0 0 = AND 0 1 = OR 1 0 = NOR 1 1 = NAND Demodulation Mode 0 0 = Falling Edge Detection 0 1 = Rising Edge Detection 1 0 = Both Edge Detection 1 1 = Reserved Transmit Mode 0 = P36 as Port Output * 1 = P36 as T8/T16_OUT Demodulation Mode 0 = P31 as Demodulator Input 1 = P20 as Demodulator Input Transmit/Demodulation Modes 0 = Transmit Mode * 1 = Demodulation Mode
Note: Care must be taken in differentiating transmit mode from demodulation mode. Depending on which of these two modes is operating, the CTR1 bit has different functions.
Note: Changing from one mode to another cannot be done without disabling the counter/timers.
* Default setting after reset
Figure 14. T8 and T16 Common Control Functions--(0D) 1H: Read/Write
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CTR2 (0D) 02H D7 D6 D5 D4 D3 D2 D1 D0 0 = P35 is Port Output * 1 = P35 is TC16 Output 0 = Disable T16 Time-out Interrupt 1 = Enable T16 time-out Interrupt 0 = Disable T16 Data Capture Interrupt 1 = Enable T16 Data Capture Interrupt 00 = SCLK on T16 01 = SCLK/2 on T16 10 = SCLK/4 on T16 11 = SCLK/8 on T16 R = 0 No T16 Time-out R = 1 T16 Time-out Occurs W = 0 No Effect W = 1 Reset Flag to 0 Transmit Mode 0 = Modulo-N for T16 1 = Single Pass for T16 Demodulator Mode 0 = T16 Recognizes Edge 1 = T16 Does Not Recognize Edge R = 0 T16 Disabled * R = 1 T16 Enabled W = 0 Stop T16 W = 1 Enable T16
* Default setting after reset
Figure 15. T16 Control Register--(0D) 2H: Read/Write Except Where Noted
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Expanded Register File Control Registers (0F) Figure 16 through Figure 29 show the expanded register file control registers (0F).
SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 = OFF ** 1 = ON Reserved (must be 0) Stop-Mode Recovery Source 000 = POR Only * 001 = Reserved 010 = P31 011 = P32 100 = P33 101 = P27 110 = P2 NOR 0-3 111 = P2 NOR 0-7 Stop Delay 0 = OFF 1 = ON* Stop Recovery Level *** 0 = Low * 1 = High Stop Flag 0 = POR * 1 = Stop Recovery ** * Default setting after reset ** Default setting after reset and Stop-Mode Recovery *** At the XOR gate input
Figure 16. Stop-Mode Recovery Register--(0F) 0BH: D6-D0 = Write Only, D7 = Read Only
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SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (must be 0) Reserved (must be 0) Stop-Mode Recovery Source 000 = POR Only * 001 = NAND P20, P21, P22, P23 010 = NAND P20, P21, P22, P23, P24, P25, P26, P27 011 = NOR P31, P32, P33 100 = NAND P31, P32, P33 101 = NOR P31, P32, P33, P00, P07 110 = NAND P31, P32, P33, P00, P07 111 = NAND P31, P32, P33, P20, P21, P22 Reserved (must be 0) Recovery Level ** 0 = Low * 1 = High Reserved (must be 0) * Default setting after reset ** At the XOR gate input Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
Figure 17. Stop-Mode Recovery Register 2--(0F) 0DH: D2-D4, D6 Write Only
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WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 = 7.5 ms min 01* = 7.5 ms min 10 = 15 ms min 11 = 60 ms min
WDT during HALT 0 = OFF 1 = ON* WDT during STOP 0 = OFF 1 = ON* Reserved (must be 0) * Default setting after reset
Figure 18. Watch-Dog Timer Register--(0F) 0FH: Write Only
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37, Standard Output* 1 P34, P37, Comparator Output Reserved (must be 1) Port 0 0 = Open-drain 1 = Push-pull* Reserved (must be 1) *Default setting after reset
Figure 19. Port Configuration Register (PCON)--(0F) 0H: Write Only
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R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 P27-P20 I/O Definition 0 = Defines bit as OUTPUT
1 = Defines bit as INPUT *
*Default setting after reset
Figure 20. Port 2 Mode Register--F6H: Write Only
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 0 = Port 2 Open-Drain * 1 = Port 2 Push-Pull 0 = P31, P32 Digital Mode 1 = P31, P32 Analog Mode Reserved (must be 0) *Default setting after reset
Figure 21. Port 3 Mode Register--F7H: Write Only
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R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode 0: Output 1: Input * Reserved; must be 0 Reserved; must be 1
Reserved; must be 0 P07-P04 Mode 0: Output 1: Input * Reserved; must be 0 * Default setting after reset
Figure 22. Port 0 and 1 Mode Register (F8h: Write Only)
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R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 = Reserved 001 = C>A>B 010 = A>B>C 011 = A>C>B 100 = B>C>A 101 = C>B>A 110 = B>A>C 111 = Reserved IRQ1, IRQ4, Priority (Group C) 0 = IRQ1>IRQ4 1 = IRQ4>IRQ1 IRQ0, IRQ2, Priority (Group B) 0 = IRQ2>IRQ0 1 = IRQ0>IRQ2 IRQ3, IRQ5, Priority (Group A) 0 = IRQ5>IRQ3 1 = IRQ3>IRQ5 Reserved (must be 0)
Figure 23. Interrupt Priority Register--F9H: Write Only
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P23 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 Inner Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11
Figure 24. Interrupt Request Register--FAH: Read/Write
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R251 IMR D7 D6 D5 D4 D3 D2 D1 D0 1 = Enables IRQ5-IRQ0 (D0 = IRQ0) Reserved (must be 0) 0 = Master Interrupt Disable * 1 = Master Interrupt Enable ** * Default setting after reset ** Only by using E1, D1 instruction. D1 is required before changing the IMR register.
Figure 25. Interrupt Mask Register--FBH: Read/Write
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 26. Flag Register--FCH: Read/Write
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R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Pointer Default setting after reset = 0000 0000 Working Register Pointer
Figure 27. Register Pointer--FDH: Read/Write
R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 General-Purpose Register Byte (SP15-SP8)
Figure 28. Stack Pointer High--FEH: Read/Write
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Lower Byte (SP7-SP0)
Figure 29. Stack Pointer Low--FFH: Read/Write
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, and 16 control and status registers (R0-R3, R4-R239, and R240-255, respectively). Additionally, there are two expanded registers groups in Banks D and F. Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the Register Pointer (Figure 30). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Working register group E0-EF can only be accessed through working registers and indirect addressing modes.
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r7 r6
r5
r
4
r3 r
2 r1 r0
R253
The upper nibble of the register file address provided by the register pointer specifies the active working-register group 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F Register Group 1 10 0F 00 Register Group 2 I/O Ports R15 to R0 R15 to R4* R3 to R0*
Specified Working Register Group
The lower nibble of the register file address provided by the Instruction points to the specified register
Figure 30. Register Pointer
Stack
The Z86L88 internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides in the general-purpose registers (R4-R239). SPH is used as a general-purpose register only when using internal stacks.
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Counter/Timer Registers
Table 9 describes the expanded register group D.
Table 9. Expanded Register Group D (D)0Ch (D)0Bh (D)0Ah (D)09h (D)08h (D)07h (D)06h (D)05h (D)04h (D)03h (D)02h (D)01h (D)00h LVD HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0
HI8(D)0Bh This register (Table 10) holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 1.
Table 10. HI8(D)0Bh Field T8_Capture_HI Bit Position 76543210 R W Description Captured Data No Effect
L08(D)0Ah This register (Table 11) holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 0HI16(D)09h.
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.
Table 11. L08(D)0Ah Field T8_Capture_L0 Bit Position 76543210 R W Description Captured Data No Effect
HI16(D)09h This register (Table 12) holds the captured data from the output of the 16-bit Counter/Timer16. This register also holds the MS-Byte of the data.
Table 12. HI16(D)09h Field T16_Capture_HI Bit Position 76543210 R W Description Captured Data No Effect
L016(D)08h This register (Table 13) holds the captured data from the output of the 16-bit Counter/Timer16. This register also holds the LS-Byte of the data.
Table 13. L016(D)08h Field T16_Capture_LO Bit Position 76543210 R W Description Captured Data No Effect
TC16H(D)07h Table 14 describes the Counter/Timer2 MS-Byte Hold Register.
Table 14. TC16H(D)07h Field Bit Position R/W Description Data
T16_Data_HI 76543210
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TC16L(D)06h Table 15 describes the Counter/Timer2 LS-Byte Hold Register.
Table 15. TC16L(D)06h Field Bit Position R/W Description Data
T16_Data_LO 76543210
TC8H(D)05h Table 16 describes the Counter/Timer8 High Hold Register.
Table 16. TC8H(D)05h Field T8_Level_HI Bit Position 76543210 R/W Description Data
TC8L(D)04h Table 17 describes the Counter/Timer8 Low Hold Register.
Table 17. TC8L(D)04h Field T8_Level_LO Bit Position 76543210 R/W Description Data
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CTR0 Counter/Timer8 Control Register Table 18 describes the CTR0 (D)00 Counter/Timer8 Control Register.
Table 18. CTR0 (D)00 Counter/Timer8 Control Register Field T8_Enable Bit Position 7------R W Single/Modulo-N Time_Out -6--------5-----R/W R W T8 _Clock ---43--R/W Value 0* 1 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 0* 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34
Capture_INT_MASK -----2-Counter_INT_Mask ------1P34_Out
Note:
R/W R/W R/W
-------0
* Indicates the value upon Power-On Reset.
T8 Enable This field enables T8 when set (written) to 1. Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 must be written to this location.
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Caution:
Writing a 1 is the only way to reset the Terminal Count status condition. Therefore, you must reset this bit before using/enabling the counter/timers. The first clock of T8 might not exhibit complete clock width and can occur anytime when enabled.
Note: Care must be taken when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (demodulation mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. For example, when the status of bit 5 is 1, a timer reset condition occurs. T8 Clock This bit defines the frequency of the input signal to T8. Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a time-out. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output.
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Common Control Register to Counter/Timer T8 and T16 This register controls the functions in common with the T8 and T16. See Table 19.
Table 19. CTR1(D)01h Register Field Mode P36_Out/Demodulator_Input Bit Position 7-------6-----R/W R/W 0* 1 0 1 T8/T16_Logic/Edge _Detect --54---R/W 00 01 10 11 00 01 10 11 Transmit_Submode/Glitch_Filter ----32-R/W 00 01 10 11 00 01 10 11 Value 0* Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved
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Table 19. CTR1(D)01h Register (Continued) Field Initial_T8_Out/Rising_Edge Bit Position ------1R/W 0 1 0 1 0 1 0 1 0 1 0 1 Value Description Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0
R W Initial_T16_Out/Falling_Edge -------0 R/W
R W
Note:
*Default upon Power-On Reset
Mode If it is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. P36_Out/Demodulator_Input In transmit mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In demodulation mode, this bit defines whether the input signal to the counter/timers is from P20 or P31. T8/T16_Logic/Edge_Detect In transmit mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In demodulation mode, this field defines which edge needs to be detected by the edge detector. Transmit_Submode/Glitch_Filter In transmit mode, this field defines whether T8 and T16 are in the "Ping-Pong" mode or in independent normal operation mode. Setting this field to "Normal
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Operation Mode" terminates the "Ping-Pong Mode" operation. When this field is set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In demodulation mode, this field defines the width of the glitch that needs to be filtered out. Initial_T8_Out/Rising_Edge In transmit mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 must be written to this location. Initial_T16 Out/Falling_Edge In transmit mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 must be written to this location. Note: Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT.
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CTR2 Counter/Timer16 Control Register Table 20 describes the contents of the CTR2 register.
Table 20. CTR2 (D)02h: Counter/Timer16 Control Register Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0 1 0 1 Time_Out --5----R W T16 _Clock ---43--R/W 0 1 0 1 00 01 10 11 0 1 0 0* 1 Value 0* 1 0 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35
Capture_INT_Mask Counter_INT_Mask P35_OUT
Note:
-----2-------1-------0
R/W R/W R/W
* Indicates the value upon Power-On Reset.
T16_Enable This field enables T16 when set to 1. Single/Modulo-N In transmit mode, when this bit is set to 0, the counter reloads the initial value when the terminal count is reached. When this bit is set to 1, the counter stops when the terminal count is reached.
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In demodulation mode, when this bit is set to 0, T16 captures and reloads on detection of all the edges. When this bit is set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see "T16 Demodulation Mode" on page 51. Time_Out This bit is set when T16 times out (terminal count reached). To reset this bit, a 1 must be written to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. Counter_INT_Mask This bit is set to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output.
Counter/Timer Functional Blocks
The following are the counter/timer functional blocks:
* * * *
Input circuit Eight-bit counter/timer circuits (page 44) Sixteen-bit counter/timer circuits (page 50) Output circuit (page 54)
Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5- D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 31).
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CTR1 D5, D4
P31 MUX P20 Glitch Filter Edge Detector
Pos Edge Neg Edge
CTR1 D6 CTR1 D3, D2
Figure 31. Glitch Filter Circuitry
Eight-Bit Counter/Timer Circuits Figure 32 shows the 8-bit counter/timer circuits.
Z8 Data Bus CTR0 D2 Pos Edge Neg Edge HI8 CTR0 D4, D3 Clock Select Clock 8-Bit Counter T8 T8_OUT LO8 CTR0 D1 IRQ4
SCLK
TC8H Z8 Data Bus
TC8L
Figure 32. 8-Bit Counter/Timer Circuits
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T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter (see Figure 33). In Single-Pass Mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, and the time-out status bit (CTR0 D5) is set. A time-out interrupt can be generated if it is enabled (CTR0 D1). See Figure 34. In Modulo-N Mode, upon reaching the terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and generates an interrupt if enabled (CTR0 D1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 35.
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T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0, D7 Yes
Reset T8_Enable Bit
CTR1, D1 Value Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Set Time-out Status Bit (CTR0, D5) and generate Timeout_Int if enabled
Enable T8
No
T8_Timeout Yes
Single Pass
Single Pass? Modulo-N
1
T8_OUT Value
0
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Enable T8
Set Time-out Status Bit (CTR0, D5) and generate Timeout_Int if enabled
No
T8_Timeout Yes
Figure 33. Transmit Mode Flowchart
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TC8H Counts
Counter Enable Command, T8_OUT switches to its initial value (CTR1 D1)
T8_OUT toggles Time-out Interrupt
Figure 34. T8_OUT in Single-Pass Mode
T8_OUT Toggles T8_OUT Counter Enable Command, T8_OUT switches to its initial value (CTR1 D1) TC8L TC8H TC8L TC8H TC8L
Time-out Interrupt
Time-out Interrupt
Figure 35. T8_OUT in Modulo-N Mode
You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. To ensure known operation, do not write these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed (a nonfunction occurs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh. Note: "h" is used for hexadecimal values. Transition from 0 to FFh is not a time-out condition. Caution: Do not use the same instructions for stopping the counter/ timers and setting the status bits.
Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. T8 Demodulation Mode You need to program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if
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it is a negative edge, HI8. From that point, an edge-detect status bits (CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the time-out status bit (CTR0 D5) is set, an interrupt can be generated if enabled (CTR0 D1), and T8 continues counting from FFh (see Figure 36 and Figure 37).
T8 (8-Bit) Count Capture
No
T8_Enable (Set by User) Yes
No
Edge Present Yes
What Kind of Edge Pos Neg T8 HI8
T8 LO8
FFh T8
Figure 36. Demodulation Mode Count Capture Flowchart
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T8 (8-Bit) Demodulation Mode
No
T8 Enable CTR0, D7 Yes FFh TC8
No
First Edge Present Yes
Disable T8
Enable TC8
No T8_Enable Bit Set Yes No
Edge Present Yes Set Edge Present Status Bit and Trigger Data Capture Int. if enabled
T8 Time-out Yes Set Edge Present Status Bit and Trigger Time Out Int. if enabled
No
Continue Counting
Figure 37. Demodulation Mode Flowchart
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Sixteen-Bit Counter/Timer Circuits Figure 38 shows the 16-bit counter/timer circuits.
Z8 Data Bus CTR2 D2 Pos Edge Neg Edge HI16 CTR2 D4, D3 Clock Select Clock 16-Bit Counter T16 LO16 CTR2 D1 IRQ3
SCLK
T16_OUT
TC16H Z8 Data Bus
TC16L
Figure 38. 16-Bit Counter/Timer Circuits
T16 Transmit Mode In Normal or Ping-Pong Mode, the output of T16, when not enabled, is dependent on CTR1, D0. If the result is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3, D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1 D0). When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. Note: Global interrupts override this function as described in "Interrupts" on page 54. If T16 is in Single-Pass Mode, T16 is stopped at this point (see Figure 39). If T16 is in Modulo-N Mode, T16 is loaded with TC16H * 256 + TC16L and the counting continues (see Figure 40).
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TC16H*256+TC16L Counts
Counter Enable Command, T16_OUT switches to its initial value (CTR1 D0)
T16_OUT toggles Time-out Interrupt
Figure 39. T16_OUT in Single-Pass Mode
TC16H*256+TCl16 T16_OUT
TC16H*256+TCl16 TC16H*256+TCl16
Counter Enable Command, T16_OUT switches to its initial value (CTR1 D0)
T16_OUT Toggles, Time-out Interrupt
T16_OUT Toggles, Time-out Interrupt
Figure 40. T16_OUT in Modulo-N Mode
You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. To ensure known operation, do not load these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a time-out condition. T16 Demodulation Mode You need to program TC16L and TC16H to FFh. After T16 is enabled and the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. If D6 of CTR2 Is 0 When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is detected during counting, the current count in T16 is one's complemented and put into HI16 and LO16. When data is captured, one of the edge-detect status bits (CTR1 D1, D0) is set, and an interrupt is generated if enabled (CTR2 D2). From that point, T16 is loaded with FFFFh and starts again. This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks).
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If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A time-out of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 and then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both, depending on CTR1 D5, D4) but continues to ignore subsequent edges. This T16 mode is generally used to measure mark times, the length of active carrier signal bursts. When T16 reaches 0, it continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt time-out can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode (see Figure 41) is only valid in transmit mode. T8 and T16 must be programmed in Single-Pass Mode (CTR0 D6, CTR2 D6), and Ping-Pong Mode must be programmed in CTR1 D3 and D2. You can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. Note: Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and then reset the status flags before instituting this operation.
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Enable
TC8
Time-out
Enable Ping-Pong CTR1, D3, D2 TC16 Time-out
Figure 41. Ping-Pong Mode
Starting Ping-Pong Mode First, make sure both counter/timers are not running. Then set T8 into SinglePass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set the Ping-Pong Mode (CTR1 D2, D3). These instructions do not have to be in any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or T16 (CTR2 D7). During Ping-Pong Mode The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) are set and cleared alternately by hardware. The time-out bits (CTR0 D5, CTR2 D5) are set every time the counter/timers reach the terminal count.
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Output Circuit Figure 42 shows the output circuit.
P34_INTERNAL MUX P34
CTR0 D0 P36_INTERNAL T8_OUT T16_OUT CTR1 D2 MUX AND/OR/NOR/NAND Logic MUX P36
CTR1 D6 CTR1 D3 CTR1 D5, D4 P35_INTERNAL MUX P35
CTR2 D0
Figure 42. Output Circuit
Interrupts
The Z86L88 features five different interrupts. The interrupts are maskable and prioritized, as shown in Figure 43. The five sources are divided as follows: three sources are claimed by Port 3 lines P33-P31and two by the counter/timers (see Table 21). The Interrupt Mask Register, globally or individually, enables or disables the five interrupt requests.
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P31 P32
P33
IRQ Register D6, D7 IRQ2
Interrupt Edge Select IRQ0 IRQ1
Timer 16 IRQ3
Timer 8 IRQ4
Low Voltage Detection IRQ5
IRQ
IMR 5 IPR Global Interrupt Enable Interrupt Request Priority Logic
Vector Select
Figure 43. Interrupt Block Diagram
Table 21. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 Source P32 P33 P31, TIN T16 T8 Vector Location Comments 0,1 2,3 4,5 6,7 8,9 External (P32), Rising Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising Falling Edge Triggered Internal Internal
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When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. As a result, all subsequent interrupt are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Z86L88 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered; all are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 22.
Table 22. IRQ Register * IRQ D7 0 0 1 1
Notes:
Interrupt Edge D6 0 1 0 1 IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F
F = Falling Edge R = Rising Edge *In stop mode, the comparators are turned off.
Clock
The Z86L88 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input; XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The Z86L88 on-chip oscillator can be driven with a low-cost RC network or other suitable external clock source.
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For 32-kHz crystal operation, an external feedback resistor (Rf) and a serial resistor (Rd) are required. See Figure 44.
XTAL1 C1 XTAL2 C2 Ceramic Resonator or Crystal C1, C2 = 47pF TYP* f = 8 MHz C2 LC C1, C2 = 22 pF L = 130 H* f = 3 MHz* XTAL1 RC @ 3V VCC (TYP) C1 = 33 pF* R = 1K* C1 L XTAL2 XTAL1 C1 R XTAL2 XTAL1
C1
Rf
XTAL1
XTAL2 C2 Rd
XTAL2 External Clock
32 kHz XTAL C1 = 20 pF, C = 33 pF Rd = 56-470K Rf = 10M
Figure 44. Oscillator Configuration
The crystal needs to be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (see Figure 44).
Power-On Reset (POR)
A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions:
* * *
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Z86L88 Low-Voltage IR Microcontroller
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The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC, and LC oscillators).
HALT
HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT.
STOP
This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A or less. STOP Mode is terminated only by a reset (such as WDT time-out), POR, SMR, or external reset. This termination causes the processor to restart the application program at address 000CH. To enter STOP (or HALT) mode, you need to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To execute this action, you must execute a NOP (op code = FFH) immediately before the appropriate sleep instruction. For example:
FF 6F NOP STOP ; clear the pipeline ; enter STOP Mode
or
FF 7F NOP HALT ; clear the pipeline ; enter HALT Mode
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Port Configuration Register (PCON)
The PCON register configures the comparator output on Port 3. It is located in the expanded register 2 at Bank F, location 00, as shown in Figure 45.
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37, Standard Output* 1 P34, P37, Comparator Output Reserved (must be 1) Port 0 0 = Open-drain 1 = Push-pull* Reserved (must be 1) *Default setting after reset
Figure 45. Port Configuration Register (PCON)--Write Only
Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the port to its standard (/O configuration. Port 0 Output Mode (D2) Bit 2 controls the output mode of Port 0. A 1 in this location set the output to pushpull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of StopMode Recovery (Figure 46). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the XORgate input is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4, or the SMR register specify the source of the StopMode Recovery signal. Bit D0 determines if SCLK/TCLK (shown in Figure 47) are divided by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0BH.
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SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 = OFF 1 = ON Reserved (must be 0) Stop-Mode Recovery Source 000 = POR Only * 001 = Reserved 010 = P31 011 = P32 100 = P33 101 = P27 110 = P2 NOR 0-3 111 = P2 NOR 0-7 Stop Delay 0 = OFF 1 = ON * Stop Recovery Level *** 0 = Low * 1 = High Stop Delay 0 = POR * 1 = Stop Recovery ** * Default setting after reset ** Default setting after reset and Stop-Mode Recovery *** At the XOR gate input
Figure 46. Stop-Mode Recovery Register
OSC
Divide by 2
Divide by 16
SCLK SMR, D0 TCLK
Figure 47. SCLK Circuit
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SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a Divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0. Stop-Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the STOP recovery (Figure 48 and Table 23 on page 63).
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SMR D4 D3 D2 000 VCC SMR D4 D3 D2 010 P31 S1 SMR D4 D3 D2 011 P32 S2 SMR D4 D3 D2 100 P33 S3 To IRQ1 S4 SMR D4 D3 D2 101 P27 SMR D4 D3 D2 110 P31 P32 P33 P20 P27 P20 P23 VCC
SMR D4 D3 D2 000
SMR D4 D3 D2 001
SMR D4 D3 D2 010
SMR D4 D3 D2 011
SMR D4 D3 D2 100 P31 P32 P33 SMR D4 D3 D2 101 P31 P32 P33 P00 P07 SMR D4 D3 D2 110 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 P22
P20 P23
SMR D4 D3 D2 111 P20 P27 SMR D6
SMR D4 D3 D2 111
To RESET and WDT Circuitry (Active Low)
SMR2 D6
Figure 48. Stop-Mode Recovery Source
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Table 23. Stop-Mode Recovery Source SMR:432 D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27
Note: Any Port 2 bit defined as an output drives the corresponding input to the default state to allow the remaining inputs to control the AND/OR function. Refer to "Stop-Mode Recovery Register 2 (SMR2)" on page 64 for other recover sources. Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5-ms RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the "fast" wake up is selected, the StopMode Recovery source must be kept active for at least 5TpC. Stop-Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86L88 from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device is reset other than Stop-Mode Recovery (SMR).
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Stop-Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop-Mode Recovery for SMR2 (see Figure 49).
SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (must be 0) Reserved (must be 0) Stop-Mode Recovery Source 2 000 = POR Only * 001 = NAND P20, P21, P22, P23 010 = NAND P20, P21, P22, P33, P24, P25, P26, P27 011 = NOR P31, P32, P33 100 = NAND P31, P32, P33 101 = NOR P31, P32, P33, P00, P07 110 = NAND P31, P32, P33, P00, P07 111 = NAND P31, P32, P33, P20, P21, P22 Reserved (must be 0) Recovery Level ** 0 = Low * 1 = High Reserved (must be 0) * Default setting after reset ** At the XOR gate input Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
Figure 49. Stop-Mode Recovery Register 2--(0F) DH:D2-D4, D6 Write Only
If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop-Mode Recovery. Note: Port pins configured as outputs are ignored as a SMR or SMR2 recovery source. For example, if the NAND or P23-P20 is selected as the recovery source and P20 is configured as an output, the remaining SMR pins (P23-P21) form the NAND equation. Table 24 describes the contents of the Stop-Mode Recovery register 2.
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Table 24. SMR2(F)0Dh: Stop-Mode Recovery Register 2 Field Reserved Recovery Level Reserved Source Bit Position 7-------6-------5-------432-W W Value 0 0* 1 0 000* 001 010 011 100 101 110 111 00 Description Reserved (Must be 0) Low High Reserved (Must be 0) A. POR Only B. NAND of P23-P20 C. NAND or P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22-P20 Reserved (Must be 0)
Reserved
Notes:
------10
*Indicates the value upon Power-On Reset Port pins configured as outputs are ignored as a SMR recovery source.
Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable, one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is selected with bit 4 of the WDT register. Bits 0 and 1 control a tap circuit that determines the minimum time-out period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits 5 through 7 are reserved (Figure 50). This register is accessible only during the first 61 processor cycles (122 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 50). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0FH. The WDTMR is organized as shown in Figure 50.
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WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 = 7.5 ms min 01* = 7.5 ms min 10 = 15 ms min 11 = 60 ms min
WDT during HALT 0 = OFF 1 = ON* WDT during STOP 0 = OFF 1 = ON* Reserved (must be 0) * Default setting after reset
Figure 50. Watch-Dog Timer Mode Register--Write Only
WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 25.
Table 25. WDT Time Select* D1 0 0 1 1 Notes:
*TpC = XTAL clock cycle. The default on reset is 10 ms.
D0 0 1 0 1
Time-Out of Internal RC OSC 7.5 ms min 7.5 ms min 15 ms min 60 ms min
WDTMR During HALT (D2) This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. The default is 1.
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WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP Mode. Since the XTAL clock is stopped during STOP Mode, the on-board RC has to be selected as the clock source to the WDT/POR counter. A 1 indicates active during STOP. The default is 1. Clock Source for WDT (D4) This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed, and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator. See Figure 51.
5 Clock Filter
*CLR2 CLK
18 Clock Reset Generator
Reset
Internal Reset Active High
WDT TAP SELECT
Ck source Select (WDTMR) XTAL Internal RD OSC. VDD VBO/VLV 2V Ref. WDT 12 ns Glitch Filter From Stop Mode Recovery Source Stop Delay Select (SMR) *CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low-to-High input translation. + - M U X
POR 7.5 ms 7.5 ms 15 ms 60 ms CLK WDT/POR Counter Chain *CLR1
Low Operating Voltage Det.
VCC
Figure 51. Resets and WDT
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Mask Selectable Options
There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 26.
Table 26. Mask Selectable Options RC/Other 32 kHz XTAL Port 0: 0-3 pull-ups Port 0: 4-7 pull-ups Port 2: 2-7 pull-ups Port 3: pull-ups Port 0: 0-3 Mouse Mode 0.4 VDD Trip RC/XTAL On/Off On/Off On/Off On/Off On/Off On/Off
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Ordering Information
Figure 52 shows the 28-pin SOIC package diagram. Figure 53 shows the 28-pin DIP package diagram. Figure 54 shows the 28-pin SSOP package diagram.
Figure 52. 28-Pin SOIC Package Diagram
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Figure 53. 28-Pin DIP Package Diagram
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Figure 54. 28-Pin SSOP Package Diagram
Z86L88
8.0 MHz 28-Pin DIP Z86L8808PSC Z86L8808PSG 28-Pin SOIC Z86L8808SSC Z86L8808SSG Note: For the die form, please contact Maxim. For fast results, contact your local Maxim sales office for assistance in ordering the part desired.
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Codes
Figure 55 shows an example of what the ordering codes represent.
Example:
Z 86L88 08 P S C is a Z86L88, 8 MHz, DIP, 0 C to 70 C, Plastic Standard Flow
Environmental Flow Temperature Package Speed Product Number Maxim Prefix Figure 55. Ordering Codes Example
Package P = Plastic DIP S = SOIC (Small Outline Integrated Circuit) Temperature S = 0 C to +70 C Speed 8 = 8.0 MHz Environmental C = Plastic Standard G = Lead free
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Customer Feedback
For any comments, detail technical questions, or reporting problems, please visit Maxim's Technical Support at https://support.maxim-ic.com/micro.
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